In static random access memories (SRAMs) there are typically two cross-coupled transistors, two pass transistors, and two resistors. The circuit diagram of SRAMs which use this typical two resistor approach is shown in FIG. 1. Memory cell 10 comprises cross-coupled N channel transistors 11 and 12, resistors 13 and 14, and N channel pass transistors 16 and 17. Pass transistors 16 and 17 are for coupling data stored by cross-coupled transistors 11 and 12 and resistors 13 and 14 to bit lines D and D, respectively, in the form of complementary signals in the read mode. In the write mode, data from the bit lines are coupled to memory cell 10 via pass transistors 16 and 17. Pass transistors 16 and 17 are both coupled to a word line WL, which when active, enables transistors 16 and 17 for the purpose of performing their coupling function. Memory cell 10 also has nodes 18 and 19. Nodes 18 and 19 provide data to bit lines D and D, respectively, when word line WL is enabled. Connected to node 18 are the gate of transistor 12, drain of transistor 11, a first terminal of resistor 13, and a current electrode of pass transistor 16. Similarly for node 19, the gate of transistor 11, the drain of transistor 12, a terminal of resistor 14, and a current electrode of transistor 17 are connected thereto. The sources of transistors 11 and 12 are connected to a negative power supply terminal which is typically ground. Second terminals of resistors 13 and 14 are connected to a positive power supply terminal V.sub.CC for receiving, for example, 5 volts. Transistors 11 and 12 act as pull-down transistors, and transistors 16 and 17 act as pass transistors.
Cell 10 stores a logic state based on the voltages at nodes 18 and 19 which also corresponds to the relative conductivities of transistors 11 and 12. A logic high is stored if node 18 is at a relatively high voltage and node 19 is at relatively low voltage. A logic low is stored if node 19 is at a relatively high voltage and node 18 is a relatively low voltage. The transistor which is conductive of transistors 11 and 12 is effective in drawing its drain to at or very near ground potential. The relatively high voltage, however, is significantly less than the voltage at V.sub.CC due to the voltage division between the relatively non-conductive transistor and the resistor to which its drain is connected. Resistors 13 and 14 are desirably very high resistance to minimize standby current. This very high resistance, however, has the effect of causing the node which is at the relatively high voltage to be reduced because of the leakage current through the transistor which is non-conductive. The voltage difference between nodes 18 and 19 is thus significantly less than that between the voltage at V.sub.CC and ground. The logic state stored in cell 10 is thus less stable than might be expected from a cross-coupled transistor pair.
Soft errors in dynamic random access memories (DRAMs) has been understood for quite some time as being caused primarily by the capacitor of one of the DRAM cells being struck by an alpha particle. The same phenomenon also occurs in SRAMs. An alpha particle striking one of the storage nodes, such as one of nodes 18 and 19, can cause the voltage on the storage node which is struck to change voltage sufficiently to cause the memory cell to change logic states. This is called a soft error. The amount of voltage change for a given alpha particle hit is inversely proportional to the capacitance on the storage node. Thus, a relatively large capacitance on the storage node reduces the amount of voltage change for a given alpha particle hit and accordingly reduces the changes of a soft error. Unfortunately, as the geometries are reduced, the capacitances on the storage nodes are also reduced. Thus, the propensity for soft errors increases as the device sizes are scaled down. There is thus an advantage to increasing the capacitance of a SRAM storage node. Such increase should not, however, increase the size of the memory. An increase in cell size would at least in part defeat the purpose of reduced geometries.